1. Field of the Invention
Embodiments described herein are directed to data networks. In particular, embodiments described herein relate to transmitting data from several data sources to several destinations.
2. Related Art
The increased speed and volume of random access memories (RAM) between nodes in data communication networks have potentially increased the speed at which local area networks (LANs) and wide area networks (WANs) transmit data between two given points in a network. These networks typically include switches or bridges having one or more input ports for receiving packetized data from sources, and one or more output ports for transmitting data received at the input ports to physical destinations in the network.
Data switches typically employ switching fabrics which couple the input ports to the output ports. Data frames received at the input ports are typically temporarily stored in RAM at the switching fabric before being transmitted to the output port associated with a desired a destination. In large capacity switches, data frames are typically received at input ports at an aggregate rate faster than the ability of the switching fabric to write to and read from a shared RAM. The differences between the media speed and the memory speed can be accommodated by increasing the widths of the words being written to and read from memory. Here, even though media speeds increase, the width of the memories may be increased to accommodate these increases in the media speed. However, benefits of increasing memory width diminishes as memory width surpasses a minimum frame length of the ports (e.g., 64-bytes for an Ethernet frame). Accordingly, there is a need for a new switching fabric architecture to allow a data switch to support increases in media speed in transmitting data between two points in the network, and to enable switches with a large number of media connections.
To address the problem of RAM throughput limitations, data switches have employed multiple memories interconnected with a means for transmitting data from an input RAM to an output port or an output port RAM. When this transfer of data from an input RAM are scheduled using a single queue, “head-of-line blocking” condition typically arises in which data is prevented from moving through a switch to an idle output port because it must wait in the queue behind data waiting for a busy output port to become idle. There is, therefore, also a need for a switching fabric architecture which reduces the incidence of head-of-line blocking.
Data switches have typically employed crossbars for interconnecting multiple ports where each input port is coupled to any of the output ports. Integrated circuit implementations of such crossbar circuitry are typically designed for a set number of ports. Current crossbar architectures typically require a geometric increase in the number of integrated circuits to increase the number input ports beyond the size of a single crossbar chip. Accordingly, there is a need for a switching fabric architecture which can be scaled to incorporate additional numbers of input and output ports without a corresponding geometric increase in a number of integrated circuits required for transmitting data frames from the input ports to the output ports.